`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:13:30 09/02/2012
// Design Name:   TimeParameters
// Module Name:   C:/Users/Maria Victoria/workspace/TimeParameters/Verificaciontimeparameters.v
// Project Name:  TimeParameters
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: TimeParameters
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Verificaciontimeparameters;

	// Inputs
	reg Prog_Sync;
	reg [1:0] Interval;
	reg [1:0] Time_Parameter_Selector;
	reg [3:0] Time_Value;
	reg Clock;
	reg Reset_Sync;
	// Outputs
	wire [3:0] Value;
	// Instantiate the Unit Under Test (UUT)
	TimeParameters uut (
		.Prog_Sync(Prog_Sync), 
		.Interval(Interval), 
		.Time_Parameter_Selector(Time_Parameter_Selector), 
		.Time_Value(Time_Value), 
		.Value(Value), 
		.Clock(Clock), 
		.Reset_Sync(Reset_Sync)
	);

	initial begin
		// Initialize Inputs
		Prog_Sync = 0;
		Time_Parameter_Selector = 0;
		Time_Value = 1;
		Clock = 0;
		Reset_Sync = 0;
		#100;
		Reset_Sync = 1;		
		#100;
		Reset_Sync = 0;		
		Prog_Sync = 1;
		Time_Parameter_Selector = 0;		
		Time_Value = 1;
		#100;	
		Prog_Sync = 0;
		Interval = 2;
		#100;	
		Interval = 0;
		#100;	
		Interval = 1;	
		#100;		
		Reset_Sync = 1;		
		#100;
		Reset_Sync = 0;	
		Interval = 0;		
	end
   always #20 Clock <= ~Clock;      
endmodule

